This invention relates to a multicomputer architecture of the type in which a massive number of computers are connected together in parallel. More particularly, the invention relates to a building block for a multicomputer machine, which building block is in the form of a semiconductor die having formed thereon a plurality of individual microcomputers connected in parallel to a first bus on the die, each microcomputer comprising an internal bus to which are connected a microprocessor, a memory and a switch device which interconnects the internal bus to the first bus, wherein the microcomputers can be interconnected to additional components.
Multicomputers using a parallel arrangement of microcomputers have been proposed in which each microcomputer is provided on a separate semiconductor chip and all of the chips are mounted on one or more printed circuit boards and interconnected by means of a common bus provided on the printed circuit boards. Yet other arrangements have been proposed in which massive numbers of microcomputers mounted on several printed circuit boards are interconnected by various forms of sophisticated interconnection networks such as a hypercube implemented by means of numerous cables. Yet other arrangements have been proposed where a moderate number of processors sharing a common control in a single instruction multiple data mode are mounted on one physical die. These latter processor would not qualify as microprocessor since they lack some essential functionality such as autonomous instruction decoding and memory addressing.
One drawback of these prior proposal is that the physical size reduction of the multicomputers is limited. Furthermore, the cost of packaging and interconnecting multiple chips is high.
An article entitled "Hypernet: A Communication-Efficient Architecture for Constructing Massively parallel Computers" by Messrs. Hwang and Ghosh published in IEEE Transactions on Computers, Vol. C-36, No. 12, December 1987 describes a multicomputer machine which is constructed of a number of basic modules each consisting of a set of interconnected nodes which is an abstraction for a processor/memory/switch element. In one embodiment described with reference to FIG. 1(d) of the article the nodes are connected to other nodes in the same module through a common bus. Each node can also be connected to a node of another module or, in the case of a special node, directly with the outside world. As each node can, according to one interpretation, be considered a microcomputer, Hwang and Ghosh therefore discloses a building block as set down in the preamble of this application.
In the Hwang and Ghosh proposal each node has dual ports, one port for connection to the common bus and another port for communicating or linking directly with a node of another module. Moreover a special node has to be provided which, in addition to providing a port for connection to the common bus, provides a port for connection to the outside world. Thus, the Hwang and Ghosh proposal involves a great number of communication links and, moreover, different types of links (one type for node to node, another type for node to external world).
Hwang and Ghosh refer to an algorithm for message routing but this is not described in detail. However, it seems clear that such an algorithm would have to be executed as a complex software program because of the complex arrangement of communication links.
Another problem with the Hwang and Ghosh proposal is that, because communication is directly through a module, a defective processor destroys the link with another module.
The Hwang and Ghosh article states that large networked machines "may be constructed with WSI technology in the future". WSI (Wafer Scale lntegration) implies the use of a single chip. However, it is clear from the geometry of FIG. 3(b) of Hwang and Ghosh that this would not be easily accomplished.